1. Field of the Invention
The present invention relates to a driving circuit of a liquid crystal display (LCD) and a liquid crystal display driven by the same circuit, and more particularly to a driving circuit of a liquid crystal display for displaying images by liquid crystal pixels arranged in a matrix shape and a liquid crystal display driven by the same driving circuit.
2. Description of the Related Art
The conventional data driver IC for driving a liquid crystal display includes one having the structure shown in FIG. 9. The data driver IC 510 shown in FIG. 9 is used for an LCD of a simple matrix format with no active component disposed on a matrix-shaped liquid crystal pixel portion, which aims to reduce power consumption, by reading out image data from a frame memory 520 for image data integrated in an IC chip.
This data driver IC 510 comprises one hundred sixty data latches 530 and the same number of data latches 540 for respectively latching image data of the predetermined number of bits (for example, 160xc3x97240xc3x972 bits) from the frame memory 520, according to a signal from the logic controller 570, one hundred and sixty decoders 550 for decoding the image data from the data latches 540, and one hundred and sixty liquid crystal driving circuits 560 for supplying the image data from the decoders 550 to one hundred sixty data bus lines. The frame memory 520 includes a RAM having the capacity of storing 160xc3x97240xc3x972 bits, corresponding to a display for the space including two hundred and forty gate bus lines and one hundred and sixty data bus lines.
For example, in the structure of providing a frame memory outside of the data driver IC, image data is first converted into serial data so to be transferred to the data driver IC, in order to decrease the number of connection cables connecting the frame memory to the data driver IC, and then expanded into parallel data again by this data driver IC. This expanded portion needs speedy operation because the number of signal lines is decreased, thereby increasing the power consumption which is detrimental to the IC. Further, since the voltage is applied to the liquid crystals regardless of a change in display, the above speedy operation to transfer data is always required.
While, apparently access to the above data driver IC 510 means access to the frame memory 520 integrated therein, and since the data can be transferred from the frame memory 520 as it is, the serial transfer unit which increases the power consumption is not necessary.
In the case of a static image, since the image data is sequentially transferred only from the frame memory 520, access from the outside is not necessary. Thus, power consumption can be decreased in this data driver IC 510.
The simple matrix LCD, however, adopts a method of selecting a desired voltage from a plurality of voltage sources by the decoder 550, for displaying image tone. Therefore, there is a problem of increasing the number of the voltage sources according to an increase in the number of the image tones.
In order to solve the problem, the data driver IC having the structure shown in FIG. 10 is well known. This data driver IC 610 is used for an LCD of active matrix format with active components disposed on the pixel portion. This LCD comprises a plurality of data bus lines and gate bus lines extending in a way of mutually crossing at right angle which are disposed at least on one of the facing boards, a plurality of pixel electrodes provided on each intersection of the data bus line and gate bus line, and a plurality of active components (switching elements) for controlling signal supply to the respective pixel electrodes.
The data driver IC 610, which is to activate three hundred data bus lines, comprises a shift register 620 for fifty bits, a data register 630 for receiving the output of the shift register 620 and digital parallel data of six bits, a 6-bit latch circuit 640 for latching the output of the data register 630, a level shifter 650 for receiving the output from the latch circuit 640 and sending three hundred of output to DACs, three hundred digital analog converters (DAC) 660 corresponding to the respective output from the level shifter 650, and three hundred voltage follower circuits (buffer circuit) 670 corresponding to the respective output from the DACs 660.
The respective output of the voltage follower circuits 670 is supplied to three hundred data bus lines. Thus, digital data of an image is converted into analog data correspondingly to the multi-tone, by the data driver IC 610.
The DACs 660 and the voltage follower circuits 670 for the output stage of the data driver IC 610 may be disposed in the output stage of the data driver IC 510 of FIG. 9, thereby realizing the structure of the data driver IC capable of multi-tone display.
In the data driver IC, however, in which multi-tone display is enabled by providing the voltage follower circuits 670 and the like in the output stage, generally an operational amplifier is used for the voltage follower circuit 670, in consideration of the current supply capacity and the dynamic range. This operational amplifier is operated by flowing the constant current (idling current) inside the circuit, regardless of presence of input signals. The number of the operational amplifiers necessary for driving the LCD becomes the same as that of the data bus lines in any case. Therefore, according to an increase in the number of the data bus lines, the number of the DACs 660 and the voltage follower circuits 670 is increased, thereby increasing the total amount of the idling current and further increasing the power consumption.
In consideration of the above, an object of the present invention is to provide a driving circuit capable of driving a liquid crystal display at lower power consumption than that of the conventional one, and a liquid crystal display driven by the same driving circuit.
According to one aspect of the invention, a driving circuit for driving a liquid crystal display provided with a first board having a plurality of gate bus lines and data bus lines mutually crossing at right angle and a plurality of pixel electrodes connected and disposed in a matrix shape through switching elements in respective intersections of the gate bus lines and the data bus lines, a second board provided in a way of facing the pixel electrodes of the first board, and liquid crystal cells held between the first board and the second board, the driving circuit comprises
a frame memory which stores image data, a digital-analog converter which converts digital data from the frame memory into analog signal, a buffer circuit which performs current amplification on output of the digital-analog converter, and a controller which controls the frame memory, the digital-analog converter, and outward circuits, in reply to a logic signal from outward, in which
the total number of the digital-analog converters and the buffer circuits within the driving circuit for use in driving the liquid crystal display is less than the number of the respective data bus lines.
In the driving circuit of the liquid crystal display of the present invention, the total number of the digital analog converters and buffer circuits provided within the driving circuit can be lessened much more than the number of the data bus lines, thereby decreasing the total idling current flowing through the buffer circuits and hence decreasing the power consumption.
In the preferred construction, the image data stored in the frame memory is supplied to the digital-analog converter without being converted from parallel to serial.
In another preferred construction, the frame memory, the digital-analog converter, the buffer circuit, and the controller are formed on the same wafer.
The frame memory, the digital analog converters, the buffer circuits, and the control circuit can be formed in the same wafer, thereby making the driving circuit in compact and extremely decreasing the parasitic capacity caused by the wiring between each circuit. Therefore, it can decrease the total power consumption of the driving circuit.
In another preferred construction, the image data stored in the frame memory is supplied to the digital-analog converter without being converted from parallel to serial, and the frame memory, the digital-analog converter, the buffer circuit, and the controller are formed on the same wafer.
According to another aspect of the invention, a liquid crystal display provided with a first board having a plurality of gate bus lines and data bus lines mutually crossing at right angle and a plurality of pixel electrodes connected and disposed in a matrix shape through switching elements in respective intersections of the gate bus lines and the data bus lines, a second board provided in a way of facing the pixel electrodes of the first board, and liquid crystal cells held between the first board and the second board, the liquid crystal display comprises
a driving circuit having a frame memory which stores image data, a digital-analog converter which converts digital data from the frame memory into analog signal, a buffer circuit which performs current amplification on output of the digital-analog converter, and a controller which controls the frame memory, the digital-analog converter, and outward circuits, in reply to a logic signal from outward, in which
the total number of the digital-analog converters and the buffer circuits within the driving circuit for use in driving the liquid crystal display is less than the number of the respective data bus lines.
In the preferred construction, the image data stored in the frame memory of the driving circuit is supplied to the digital-analog converter without being converted from parallel to serial.
In another preferred construction, the frame memory, the digital-analog converter, the buffer circuit, and the controller of the driving circuit are formed on the same wafer.
In another preferred construction, the image data stored in the frame memory of the driving circuit is supplied to the digital-analog converter without being converted from parallel to serial, and the frame memory, the digital-analog converter, the buffer circuit, and the controller of the driving circuit are formed on the same wafer.
In another preferred construction, the liquid crystal display further comprises a first shift register for driving the gate bus line, a second shift register for driving the data bus line, and a plurality of analog switches respectively connected to the data bus lines.
The liquid crystal display of the present invention can obtain preferable liquid crystal display operation by sequentially supplying the output of the driving circuit to the data bus lines in a timesharing way, through analog switch groups connected to the second shift register.
In another preferred construction, output of the first shift register is connected to the respective gate bus lines, and control terminals of the analog switches, in every bundle of m pieces (m is the natural number), are connected to output of the second shift register, and the first and second shift registers are respectively controlled by a signal from the controller and output of the buffer circuit is connected to the analog switches.
In another preferred construction, the first shift register, the second shift register, and the analog switches are formed by a polysilicon thin film field-effect transistor at least on one of the first board and the second board.
In the preferred liquid crystal display of the present invention, the first shift register, the second shift register, and the analog switches are formed on at least one of the first board and the second board, by polysilicon thin film field-effect transistors. In this case, the liquid crystal display can be downsized, and the outward circuit can be reduced in size by forming a part of the circuit on the board, for example, on the glass board, thereby decreasing the cost of the liquid crystal display.
In another preferred construction, the first shift register, the second shift register, and the analog switches are formed by a polysilicon thin film field-effect transistor at least on one of the first board and the second board, output of the first shift register is connected to the gate bus lines, and control terminals of the analog switches, in every bundle of m pieces (m is the natural number), are connected to output of the second shift register, and the first and second shift registers are respectively controlled by a signal from the controller, and output of the buffer circuit is connected to the analog switches.
Other objects, features and advantages of the present invention will become clear from the detailed description given herebelow.